Bhowmik, B.Biswas, S.Deka, J.K.2026-02-062020Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, 2020, Vol.2020-October, , p. 2339-23441062922Xhttps://doi.org/10.1109/SMC42975.2020.9283106https://idr.nitk.ac.in/handle/123456789/30580With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE.coexistent manufacturing channel-faultsnondiagnosable faultson-chip communication interconnection architectureon-line fault testingperformance analysis