Rachit, I.K.Bhat, M.S.2020-03-302020-03-3020082008 International Conference on Electronic Design, ICED 2008, 2008, Vol., , pp.-https://idr.nitk.ac.in/handle/123456789/7418In this paper, we present the development of an open source tool, AutoLibGen, for characterising a standard cell library comprising of basic combinational circuits. The cells are initially laid out and the parasitic netlists are extracted. Unlike the traditional method of computing timing and power data using non linear delay and power models we use more accurate Composite Current Source (CCS) based characterization for very deep sub-micron technologies. We tested our tool with a library for 65nm. The library file generated by our tool was successfully compiled by Synopsys Library Compiler and is used to synthesize a Verilog code using Synopsys Design Compiler. �2008 IEEE.Book chapter