Sharma, M.Rahul, R.Madhusudan, S.Deepu, S.P.Sumam David, S.2026-02-062021Proceedings of the 2021 IEEE 18th India Council International Conference, INDICON 2021, 2021, Vol., , p. -https://doi.org/10.1109/INDICON52576.2021.9691658https://idr.nitk.ac.in/handle/123456789/30211For applications that require object detection to be performed in real-time, this paper presents a custom hardware accelerator, implementing state of the art Tiny YOLO-v3 algorithm. The proposed architecture achieves a reasonable tradeoff between the speed of computation (measured in frames per second or FPS) and the hardware resources required. Each CNN layer is pipelined and parameterized to make the complete design re-configurable. The proposed hardware accelerator was synthesized using the SCL(Semi-Conductor Laboratory, India) 180 nm CMOS process and also using Vivado Xilinx software with Virtex Ultrascale+ FPGA as the target device. The pipelined architecture, along with other architectural novelties, provided a higher frame-rate of 32.1 FPS and a performance of 166.4 GOPS at 200 MHz clock frequency. © 2021 IEEE.Convolutional Neural NetworkHardware acceleratorObject detectionTiny YOLO-v3YOLO