Kulkarni A.Iteesh V.A.Sahith S.R.2021-05-052021-05-052019Proceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019 , Vol. , , p. 350 - 354https://doi.org/10.1109/iSES47678.2019.00087https://idr.nitk.ac.in/handle/123456789/14948This paper looks into the modelling and analysis of on-chip interconnects in the lower metal region of an Integrated Circuit (IC). A proposed π-interconnect model is quantitatively modelled and analysed and the delay time, td is used as a metric to measure performance change from ideal circuit simulations for varying interconnect lengths using a driver-load inverter pair. The π-model delay time performance is also compared with that of a layout of an driver-load inverter pair circuit and a 3-stage ring-oscillator circuit. The layout is generated using MOSIS SCMOS technology using ON Semiconductor C5 600nm device model with VDD = 5V. All modelling and analysis is done using open-source EDA tools and technology. © 2019 IEEE.Conference Paper