Kallinatha, H.D.Talawar, B.2026-02-062023Proceedings - 2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics Workshops, HiPCW 2023, 2023, Vol., , p. 79-https://doi.org/https://idr.nitk.ac.in/handle/123456789/29256This study introduces a new approach to integrate SOT-MRAM into hybrid and full main memory architectures in a multi-core system. The study overcomes the challenge of limited publicly available SOT-MRAM parameters for reliable simulation. In this work, we conducted micro-architectural design space exploration and full system simulations to highlight the potential of SOT-MRAM. The study shows that SOT-MRAM offers remarkable power reduction, bandwidth increase, and a reduction in Energy-Delay Product (EDP) with minimal latency impact. Even with scaled current and timing parameters, SOTMRAM outperforms DRAM. This approach has opened up new possibilities for energy-efficient memory systems that could significantly improve the performance of multi-core systems. © 2023 IEEE.Hybrid MemoriesNon-volatile Memories(NVM)SOT-MRAMSTT-MRAM