Jagadish, D.N.Bhat, M.S.2020-03-302020-03-302015Journal of Low Power Electronics, 2015, Vol.11, 3, pp.436-443https://idr.nitk.ac.in/handle/123456789/8436In this paper, we propose a low energy consumption and area efficient successive approximation register analogue-to-digital converter. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array in comparison to other nonbinary capacitor array based successive approximation register analogue-to-digital converters. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside capacitor array, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. Copyright � 2015 American Scientific Publishers All rights reserved.Book chapter