Bhowmik, B.Gagan, N.2026-02-0620232023 IEEE International Test Conference India, ITC India 2023, 2023, Vol., , p. -https://doi.org/10.1109/ITCIndia59034.2023.10235563https://idr.nitk.ac.in/handle/123456789/29437A network on chip (NoC) exposes faults that disturb overall performance. Subsequently, a routing algorithm with fault tolerant facility has become a holistic aspect of reliable NoC communications. We propose a routing mechanism including fault tolerance in channels of a pseudo-3D mesh NoCs. The concept of a detour path is the foundation of the proposed solution. Its goal is to ensure the delivery of almost all packets with a detour of a few without utilizing broken or faulty communication functionalities. On evaluations, the suggested technique produces 11.47% greater throughput, 38.38% lesser latency, and 65.50% improved energy consumption compared to the baseline mesh NoC. Based on the findings, one may conclude that the proposed fault-Tolerant routing performs more effectively even at higher traffic load levels. © 2023 IEEE.Communications Circuits and SystemsE2E DeliveryFault-Tolerant RoutingNoC MetricsPseudo-3D NoC