Kuncham, S.S.Gadiyar, M.Sushmitha, Din, K.Lad, K.K.Laxminidhi, T.2020-03-302020-03-302018Proceedings of the IEEE International Conference on VLSI Design, 2018, Vol.2018-January, , pp.167-170https://idr.nitk.ac.in/handle/123456789/7085The inability to sense the transitions in the input by conventional phase frequency detector (PFD) during the reset operation leads to blind zone, which reduces the acquisition speed and the detection range. The pull down network in proposed design is modified so as to eliminate the reset pulse for phase difference beyond the dead zone in order to have a full detection range and less cycle slippage. As the design gives the right polarity for phase differences close to �2?, the acquisition time is reduced substantially. The Transfer characteristic of the PFD manifests an identical response. The PFD design is implemented in 180nm CMOS technology and consumes 1.36mW at an operating frequency of 1GHz. � 2018 IEEE.Book chapter