Lad, H.Rekha, S.Laxminidhi, T.2026-02-052020Circuits, Systems, and Signal Processing, 2020, 39, 8, pp. 3819-38320278081Xhttps://doi.org/10.1007/s00034-020-01366-1https://idr.nitk.ac.in/handle/123456789/23805This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (F<inf>max</inf>) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Charge pump circuitsPhase locked loopsBlind zonesDead zonesHigh SpeedLow PowerPhase frequency detectorsPhase comparators