Kumar, A.Talawar, B.2026-02-042022Journal of Circuits, Systems and Computers, 2022, 31, 11, pp. -2181266https://doi.org/10.1142/S0218126622501961https://idr.nitk.ac.in/handle/123456789/22501Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from 2×2 to 45×45 are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is 5000× to 5500× with respect to BookSim simulator. © 2022 World Scientific Publishing Company.Distributed computer systemsForecastingIntegrated circuit designMachine learningNetwork architectureRegression analysisRoutersServersSimulatorsAreaBooksimNetworks on chipsNoC architecturesPerformancePerformance ModelingPowerSimulationSupport vector regressionsTraffic patternNetwork-on-chip