Sravani K.Rao R.2021-05-052021-05-052021Lecture Notes in Electrical Engineering , Vol. 700 , , p. 1543 - 1548https://doi.org/10.1007/978-981-15-8221-9_144https://idr.nitk.ac.in/handle/123456789/14701This paper proposes a new way of realizing the data paths for asynchronous domino logic gate-level pipeline styles. This novel approach improves the speed of the pipelines by preserving the latch-less feature of domino pipelines. In this work, the data paths of three asynchronous 16-bit adders based on APCDP, LP2/2, and HC-Hybrid pipelines are constructed using dual-rail domino cascode voltage switch (DDCVS) logic and simulated using cadence toolset in 90 nm technology. The adders based on DDCVS logic have exhibited higher performance and lower energy-delay square product compared to the adders based on domino logic. © 2021, Springer Nature Singapore Pte Ltd.Conference Paper