Narasimaiah, J.D.Laxminidhi, T.Bhat, M.S.2026-02-052018IET Circuits, Devices and Systems, 2018, 12, 3, pp. 249-2551751858Xhttps://doi.org/10.1049/iet-cds.2017.0029https://idr.nitk.ac.in/handle/123456789/25162In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.Approximation theoryCMOS integrated circuitsDielectric devicesEnergy utilizationMetallic compoundsMetalsMOS capacitorsOxide semiconductorsTransistorsAnalogue to digital converter (ADC)Complementary metal oxide semiconductor processComplementary metal oxide semiconductorsLow energy consumptionSuccessive approximation registerSuccessive approximation register adcSwitched capacitorSwitched capacitor integratorAnalog to digital conversion