Mondal, S.Gayen, P.K.Gaonkar, D.N.2026-02-032025IEEE Transactions on Industrial Electronics, 2025, 72, 1, pp. 949-9582780046https://doi.org/10.1109/TIE.2024.3413817https://idr.nitk.ac.in/handle/123456789/20477Recent research has focused on the enhancement of the prefiltering capability of phase-locked loops (PLL). The cascaded delayed signal cancellation (CDSC) PLL removes the low-order selective harmonic frequencies near the fundamental frequency. Here, a frequency-adaptive time delay unit is used to cope with frequency and phase variations of voltage. The high-frequency signal arising due to the frequency-adaptive loop cannot be mitigated. In effect, the transient response of adaptive CDSC-PLL shows a significant irregular pattern. Therefore, this article suggests the use of a second-order generalized integrator (SOGI) after the adaptive CDSC unit to improve the transient profile of frequency response. In the design, the high gain (K = 5.4) of SOGI is chosen to quickly settle the response of PLL at the expense of its ignorance of lower-order harmonics near the fundamental frequency. However, the lower-order harmonics are selectively eliminated by the CDSC unit. So, both prefilters complement each other's filtering capabilities. Additionally, the suggested prefilter provides improved noise immunity and eliminates DC offset via the SOGI unit. The linearized model and tuning procedure for the different control parameters of the proposed PLL are described. The real-time hardware-in-loop tests are executed to justify the optimum performance of the proposed PLL. © 2024 IEEE.Computer debuggingDelay control systemsDelay lock loopsElectromagnetic transientsIntegrated circuit designPhase locked loopsSignal denoisingStructural analysisStructural dynamicsTime delayAlpha-betaAlpha-beta cascaded delayed signal cancelation (?? cascaded delayed signal cancelation)Distorted voltagesNoise immunityPhase lockedPhase-locked loopSecond order generalized integratorSecond-order generalized integratorsSignal cancellationUnbalanced voltagesTransient analysisA Fast and Robust PLL Design with a Combination of Frequency-Adaptive Alpha-Beta-CDSC and SOGI