Hanumantha Rao, G.Rekha, S.2026-02-052020International Journal of Circuit Theory and Applications, 2020, 48, 2, pp. 170-180989886https://doi.org/10.1002/cta.2726https://idr.nitk.ac.in/handle/123456789/24064This paper proposes a simple technique to increase the time constant of a log-domain filter. By using the proposed technique, the capacitor value can be reduced considerably; hence, overall area of the circuit can be reduced. A second-order log-domain low-pass filter (LPF) is implemented in UMC 65-nm complementary metal-oxide semiconductor (CMOS) technology to validate the proposed technique. It occupies an area as low as 0.005 mm2 and operates with a 0.5-V supply. For a cutoff frequency of 100 Hz, the filter consumes a power of 4 nW. By adjusting the bias current, the cutoff frequency can be linearly tuned from 10 to 500 Hz. The filter has the figure of merit (FoM) of 0.68×10?13 J, which is on par with many designs listed in the literature. The filter uses the lowest capacitance/pole (0.92 pF) among the similar designs given in the literature, which shows that the present design is area efficient. © 2019 John Wiley & Sons, Ltd.CapacitanceCMOS integrated circuitsCutoff frequencyMetalsMOS devicesOxide semiconductorsSilicon on insulator technologyLarge time constantLog domain filtersLow PowerLow voltagesLow-frequencyLow pass filters