Devika, S.Ramesh, E.Rekha, S.2026-02-0620242024 IEEE International Conference on Smart Power Control and Renewable Energy, ICSPCRE 2024, 2024, Vol., , p. -https://doi.org/10.1109/ICSPCRE62303.2024.10674983https://idr.nitk.ac.in/handle/123456789/28823In this paper, a low power semi dynamic - hybrid latch flip flop (SD-HLFF) is proposed. This circuit is a combination of semi dynamic flip flop (SDFF) and hybrid latch flip flop (HLFF). The fastest traditional hybrid structure is SDFF, but because of its huge precharge capacitance and CLK load, it is not power-efficient. Despite not being the fastest, HLFF uses less power than SDFF. However, the output node's longer stack of NMOS transistors in the case of HLFF results in a longer hold-time requirement and inferior performance compared to SDFF. Several simulations that are done on proposed FF using UMC 65nm technology, show better performance measurements than the conventional SDFF, HLFF and Dual dynamic node flip flop. © 2024 IEEE.Embedded logichybrid latch flip flopsemi dynamic flip flop