Rai, S.Talawar, B.2026-02-062024Proceedings of the IEEE International Conference on High Performance Computing, Data, and Analytics Workshops, HiPCW, 2024, Vol., 2024, p. 219-22027700151https://doi.org/10.1109/HiPCW63042.2024.00087https://idr.nitk.ac.in/handle/123456789/29202Hybrid memories comprising of DRAM-NVM or DRAM-CXL based devices are emerging as potential alternatives to overcome the drawbacks of monolithic DRAM based memories. This arrangement in the memory hierarchy will bring a paradigm shift and there is a necessity to re-look the existing policies. This work proposes an ideal page replacement policy for hybrid memories. © 2024 IEEEHybrid MemoriesInter-reference distanceNon-volatile MemoriesHistory aware interference distance based Page replacement policy for Hybrid Memory