Saranya, M.N.Sriadibhatla, S.Nagulapalli, R.2026-02-062023Smart Innovation, Systems and Technologies, 2023, Vol.313, , p. 567-57521903018https://doi.org/10.1007/978-981-19-8669-7_50https://idr.nitk.ac.in/handle/123456789/29497At the design level, meeting the performance requirement of applications demanding high gain operational transconductance amplifier (OTA) at low voltage in fine-line CMOS process technologies is a challenging task. This paper presents a split input differential pair design approach to enhance the DC gain of a standard folded cascode operational transconductance amplifier (SFCOTA). A Prototype implemented in TSMC 65 nm CMOS technology demonstrates a significant performance enhancement without additional bias circuitry and voltage headroom penalty. The transistor-level preliminary simulation in Cadence Specter shows that the proposed amplifier achieves a better DC gain of 66.2 dB and 261.5 MHz unity-gain bandwidth, outperforming existing amplifier architectures. The circuit consumes 144.8 µW with a 1 V supply making it suitable for low-voltage applications. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Dc gainDifferential pairFolded cascodeOTAUnity-gain bandwidth