Jagadish, D.N.Bhat, M.S.2020-03-302020-03-302015Proceedings - 2014 5th International Symposium on Electronic System Design, ISED 2014, 2015, Vol., , pp.54-57https://idr.nitk.ac.in/handle/123456789/8435A low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array (CA) in comparison to other nonbinary capacitor array based SAR ADCs. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside CA, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. � 2014 IEEE.Book chapter