Bhowmik B.Biswas S.Deka J.K.Bhattacharya B.B.2021-05-052021-05-052020Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI , Vol. 2020-July , , p. 200 - 205https://doi.org/10.1109/ISVLSI49217.2020.00044https://idr.nitk.ac.in/handle/123456789/14916Networks-on-chip (NoCs) provide the essential communication infrastructure for building today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying interconnection architecture, other regular topologies such as octagons or spidergons, find recent applications to hybrid, small-world, and smart networks. Aggressive technology scaling, however, makes NoCs susceptible to manufacturing defects and causes failures in their operations. This paper presents a distributed, on-line built-in-self-test (BIST) mechanism that targets open faults on communication channels in an octagon NoC. We introduce a novel test scheduling scheme that exploits the knowledge of multithreading for reducing the overall test time with minimal degradation of performance. We evaluate the proposed test scheme for a 16-bit octagon NoC and report experimental results. © 2020 IEEE.Conference Paper