Kirankumar, H.L.Rekha, S.Laxminidhi, T.2026-02-032025Circuits, Systems, and Signal Processing, 2025, , , pp. -0278081Xhttps://doi.org/10.1007/s00034-025-03454-6https://idr.nitk.ac.in/handle/123456789/20579A wide frequency range, inductor-less, charge pump phase locked loop (CP-PLL) is presented in this paper. It has a multi-phase, two stage cascaded architecture. This design uses a dead-zone free, zero blind-zone phase frequency detector (PFD) and a low mismatch charge pump (CP) circuit to generate low jitter clocks. A 3-stage single ended ring oscillator of 625 MHz VCO is designed for the first stage. An 8-phase feed-forward coupled VCO with programmable multi band ranging from 1.25 to 5 GHz is designed for the second stage of this cascaded system. Overall, this proposed cascaded PLL achieves jitter FOM and jitter-N FOM of -227.1 and ? 250.1 dB, respectively for 5 GHz output frequency with 1.44 ps rms jitter while consuming 9.24 mW of power from 1.2 V supply. This proposed clock generator circuit, designed in UMC 65 nm CMOS technology, occupies an area of 0.079 mm2. This study contributes to the development of energy-efficient, high speed clock generation solutions derived from a low reference clock. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.Electric clocksJitterLocks (fasteners)Low power electronicsPhase comparatorsVariable frequency oscillatorsCascaded phase locked loopClock generatorHigh SpeedHigh speed clock generatorLow PowerLow reference frequencyMulti-phase ring oscillator based VCOPhase lockedReference frequencyRing oscillatorPhase locked loops