Lad Kirankumar, H.Rekha, S.Laxminidhi, T.2026-02-052021Microelectronics Journal, 2021, 114, , pp. -9598324https://doi.org/10.1016/j.mejo.2021.105156https://idr.nitk.ac.in/handle/123456789/23145This paper presents a low mismatch high-speed charge pump for high bandwidth phase locked loop (PLL). A novel mismatch compensation technique is used for reducing the current mismatch without having any extra area and power overhead. Proposed circuit is designed for 100 ?A charge pump current (I<inf>CP</inf>) and it achieves less than 1% mismatch current across all process corners for an output voltage compliance range of 0.2–1 V. A prototype circuit of 1 GHz PLL is designed in 65 nm CMOS technology for testing the proposed charge pump. It achieves ?81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 ?W power from 1.2 V supply including the reference current. Area occupied by proposed design is 72 × 35 ?m2. © 2021 Elsevier LtdBandwidthPhase locked loops65 nm CMOS technologiesCharge pump currentsCurrent mismatchMismatch compensationPhase Locked Loop (PLL)Prototype circuitsReference currentsReference frequencyCharge pump circuits