Islam, M.T.Haque, M.N.Khan, S.R.Naik, J.D.Al-Shidaifat, A.D.Kumar, S.Song, H.2026-02-062023Lecture Notes in Networks and Systems, 2023, Vol.554, , p. 479-48523673370https://doi.org/10.1007/978-981-19-6661-3_43https://idr.nitk.ac.in/handle/123456789/29664Integrated digital circuits (IDCs) have become a popular option for DC–DC buck converters. This article describes a novel CMOS DC–DC buck converter architecture that leverages pulse-width modulation (PWM) for low-power technology. Double delay lines are used in the PWM power consumption which is minimized throughout design and improve unstable voltage while increasing resolution. The functioning of PWM is described using an algorithm developed. Under the working frequency of 100 kHz, the promising findings suggest that the power consumption is reduced to 1.17 W while taking up less space. With a current, the DC–DC buck converter using PWM has a high efficiency of 92.2% across a power range of 4–10 mA. Compared to traditional converters, our PWM approach reduces ripple voltage by 48% and allows in order to create within a DC–DC converter in a smaller chip area. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.CMOS DCDC buck converterDigital logic gatePWM technique for low-power circuit