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dc.contributor.authorNarasimaiah, J.D.-
dc.contributor.authorTonse, L.-
dc.contributor.authorBhat, M.S.-
dc.identifier.citationIET Circuits, Devices and Systems, 2018, Vol.12, 3, pp.249-255en_US
dc.description.abstractIn this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a 350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. 2018, The Institution of Engineering and Technology.en_US
dc.title11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductoren_US
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