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|dc.identifier.citation||International Conference and Exhibition on Device Packaging 2013, 2013, Vol., , pp.1-||en_US|
|dc.description.abstract||Stacking chips, either on a 2.5D interposer or in true 3D ICs, is an industry game changer since it promises the benefits of higher performance, functionality and density at lower power consumption. With advent of the first 2.5D products in volume production, the need to reduce cost, particularly for consumer applications, is gaining prominence. Lithographic scaling has driven performance and cost vectors in the semiconductor industry for decades. Comprehensive models, developed to understand the impact of scaling on device performance, reliability and cost, make it easier to develop scaling roadmaps. In a similar fashion, credible models for 3D interconnects are critical, since these will underpin the development of future 3D technology "nodes" by providing performance and cost estimates. The roadmaps, in turn, will drive the development of materials, equipment, EDA tools and products. This presentation will examine some of the near term manufacturability concerns as well as key areas for 3D scaling, together with the electrical and thermo-mechanical challenges that accompany them. � (2013) by IMAPS - International Microelectronics & Packaging Society All rights reserved.||en_US|
|dc.title||Keynote: 2.5 and 3D - scaling walls||en_US|
|Appears in Collections:||2. Conference Papers|
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