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https://idr.nitk.ac.in/jspui/handle/123456789/8155Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Prasad, G.R. | - |
| dc.contributor.author | Shet, K., C. | - |
| dc.contributor.author | Bhat, Narasimha, B. | - |
| dc.date.accessioned | 2020-03-30T10:18:08Z | - |
| dc.date.available | 2020-03-30T10:18:08Z | - |
| dc.date.issued | 2008 | - |
| dc.identifier.citation | Innovations and Advanced Techniques in Systems, Computing Sciences and Software Engineering, 2008, Vol., , pp.393-398 | en_US |
| dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/8155 | - |
| dc.description.abstract | This paper presents GRASP ("Greedy Reconfigurable Approach for Shortest Path"), a new shortest path algorithm using reconfigurable logic. It has time complexity O(P), where 'P' is maximum of number of edges along the shortest paths from source to other nodes. It is a modification of Bellman-Ford algorithm and is highly parallel and scalable. Unlike most other shortest path algorithms, GRASP does not need to find the minimum of nodes/adjacent nodes. Hence its FPGA implementation is faster compared to other FPGA implementations. Preliminary experimental results show that a 17-node GRASP runs about 4.7 times faster compared to parallel Bellman-Ford algorithm on Xilinx Virtex II. � Springer Science+Business Media B.V. 2008. | en_US |
| dc.title | GRASP: A greedy reconfigurable approach for shortest path | en_US |
| dc.type | Book chapter | en_US |
| Appears in Collections: | 2. Conference Papers | |
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