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Title: Floating-point adder in techology driven high-level synthesis
Authors: Joseph, M.
Bhat, N.B.
Chandra, Sekaran, K.
Issue Date: 2011
Citation: Communications in Computer and Information Science, 2011, Vol.131 CCIS, PART 1, pp.49-58
Abstract: Implementation of floating-point algorithms in fixedpoint processor asks for customization into fixed-point for that processor. Technology driven High-Level Synthesis is a customized High-Level Synthesis approach for a particular fixed-point processor. It makes the present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Synthesis become aware of target technology since parsing here. It makes right inference of hardware by attaching target technology specific attributes to the parse tree in it, which guides to generate optimized hardware. This paper, integrating both, presents an approach to synthesize the floating-point algorithms in this customized tool. It performs the conversion of floating-point model into corresponding fixed-point model and synthesizes it for implementing onto an Field Programmable Gate Array. This compiler driven approach generates optimal output in terms of silicon usage and power consumption. � Springer-Verlag Berlin Heidelberg 2011.
Appears in Collections:2. Conference Papers

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