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|dc.identifier.citation||Proceedings - 2016 6th International Symposium on Embedded Computing and System Design, ISED 2016, 2017, Vol., , pp.72-76||en_US|
|dc.description.abstract||This paper presents the design of RESURF based non-conventional LDMOS and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage Vs On-resistance Ron to enhance the suitability of the device for High Voltage I/O applications in Sub-micron RF-SoC. A breakdown voltage of 21V at a very low Ron of 2.5k? was achieved for a device gate length of 250nm and gate oxide thickness of 5nm. � 2016 IEEE.||en_US|
|dc.title||Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications||en_US|
|Appears in Collections:||2. Conference Papers|
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