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dc.contributor.authorBhat, K.G.
dc.contributor.authorLaxminidhi, T.
dc.contributor.authorBhat, M.S.
dc.identifier.citationIEEE Region 10 Annual International Conference, Proceedings/TENCON, 2016, Vol.2016-January, , pp.-en_US
dc.description.abstractThis paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 ?W from the power supply of 1V. � 2015 IEEE.en_US
dc.titleAn 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DACen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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