Please use this identifier to cite or link to this item: https://idr.nitk.ac.in/jspui/handle/123456789/7161
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dc.contributor.authorAparna, T.
dc.contributor.authorPolineni, S.
dc.contributor.authorBhat, M.S.
dc.date.accessioned2020-03-30T09:58:34Z-
dc.date.available2020-03-30T09:58:34Z-
dc.date.issued2019
dc.identifier.citation2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings, 2019, Vol., , pp.152-157en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/7161-
dc.description.abstractThe design and simulation of a low power, high gain three stage operational transconductance amplifier (OTA) is presented. This OTA has a DC gain of 73.5 dB, a unity gain bandwidth (UGB) of 39.8 MHz and a phase margin of 59�. The total power consumed by OTA is 332 ?W. The DC gain and the power dissipation parameters of the OTA are found to be better than the previously published results of [1]-[4]. Further, a first order Delta Sigma Modulator (DSM) is designed as a vehicle to test the OTA by integrating it with a comparator and a DAC for a signal bandwidth of 2 kHz with an oversampling ratio (OSR) of 250 for low frequency biomedical applications. All the blocks are designed using UMC 180nm CMOS 1P9M technology, with 1.8 V supply voltage. The simulation results show that the in-band signal to noise and distortion ratio (SNDR) of the DSM is 53 dB, which is equivalent to 8.5 effective number of bits (ENOB). � 2018 IEEE.en_US
dc.titleA Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulatoren_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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