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dc.contributor.authorShrivastava, P.-
dc.contributor.authorBhat, K.G.-
dc.contributor.authorLaxminidhi, T.-
dc.contributor.authorBhat, M.S.-
dc.identifier.citationProceedings - 2012 3rd International Conference on Emerging Applications of Information Technology, EAIT 2012, 2012, Vol., , pp.462-466en_US
dc.description.abstractThis paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18?m technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. � 2012 IEEE.en_US
dc.titleA 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADCen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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