Please use this identifier to cite or link to this item: https://idr.nitk.ac.in/jspui/handle/123456789/6949
Full metadata record
DC FieldValueLanguage
dc.contributor.authorSoorya, K.K.-
dc.contributor.authorBhat, M.S.-
dc.date.accessioned2020-03-30T09:46:28Z-
dc.date.available2020-03-30T09:46:28Z-
dc.date.issued2012-
dc.identifier.citation2012 International Conference on Devices, Circuits and Systems, ICDCS 2012, 2012, Vol., , pp.206-210en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/6949-
dc.description.abstractIn a multilayer structure of Integrated Circuit (IC) chips, clock signals are distributed through intermediate/global interconnects of clock tree network. These metal lines are very thin and offer high resistance and capacitive loading to the propagating electrical signals resulting in interconnect delay. This has significant impact on the propagation of clock signals, especially in GHz regime. In this work, we propose a Composite Right/Left Handed (CRLH) system augmenting the long metal interconnect line to reduce/remove the delay in the propagation of the clock signals. The CRLH system is shown to have minimum signal reflection at its resonant frequency and this feature is used for the transmission of high speed clock signals.We have designed a CRLH structure to resonate at 10 GHz. Simulation results show that when the clock signals are transmitted through interconnect-CRLH-interconnect system at this frequency, the propagation delay reduces almost to zero. � 2012 IEEE.en_US
dc.titleZero delay clocking system in GHz frequency regime using CRLH metamaterial structureen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

Files in This Item:
File Description SizeFormat 
6949.pdf1.45 MBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.