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dc.contributor.authorKumar, A.
dc.contributor.authorTalawar, B.
dc.identifier.citationLecture Notes in Electrical Engineering, 2020, Vol.607, , pp.723-733en_US
dc.description.abstractConventional Bus-based On-Chips are replaced by Packet-switched Network-on-Chip (NoC) as a large number of cores are contained on a single chip. Cycle accurate NoC simulators are essential tools in the earlier stages of design. Simulators which are cycle accurate performs gradually as the architecture size of NoC increases. NoC architectures need to be validated against discrete synthetic traffic patterns. The overall performance of NoC architecture depends on performance parameters like network latency, packet latency, flit latency, and hop count. Hence we propose a Unified Performance Model (UPM) to deliver precise measurements of NoC performance parameters. This framework is modeled using distinct Machine Learning (ML) regression algorithms to predict performance parameters of NoCs considering different synthetic traffic patterns. The UPM framework can be used to analyze the performance parameters of Mesh NoC architecture. Results obtained were compared against the widely used cycle accurate Booksim simulator. Experiments were conducted by varying topology size from 2�2 to 50�50 with different virtual channels, traffic patterns, and injection rates. The framework showed an approximate prediction error of 5% to 6% and overall minimum speedup of 3000� to 3500�. � Springer Nature Singapore Pte Ltd 2020.en_US
dc.titleUPM-NoC: Learning based framework to predict performance parameters of mesh architecture in on-chip networksen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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