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|Obtaining a better harmonic profile at relatively lower switching frequencies is one of the key tasks in the present day power electronics world. The pulse width modulation (PWM) techniques used in the inverter influence the harmonic content of the inverter output waveform and its switching power loss. Several PWM techniques have been developed earlier to improve the harmonic profile of the inverter output waveform. Dodecagonal space vector generation technique is one of them, which gives a better harmonic profile by eliminating the most dominant lower order harmonics, that is, fifth and seventh from the inverter output waveform. The elimination of fifth and seventh harmonics results in improvement in the quality of the output waveform and eliminates the sixth harmonic torque pulsations in the motor drives. By considering these advantages, two groups of dodecagonal space vector-based clamping PWM (DSVCPWM) techniques are developed in this report. The switching sequences in the first group use the zero vector once in every sub-cycle period. On the other hand, the second group of voltage vector sequences switch an active vector twice in every sub-cycle period. The proposed DSVCPWM techniques facilitate lowering of inverter switching power loss for lagging power factor loads and the better harmonic profile at higher modulation indices by clamping each phase to either positive or negative DC bus during different intervals in a fundamental cycle. Both groups have the same clamping durations in a fundamental cycle. However, due to the difference in their switching locations, the switching power loss will vary. Moreover, the variable clamping PWM techniques in the DSVCPWM group control the clamping location for a specific duration, which results in a lower switching power loss than C12SVPWM and other DSVCPWM techniques. In this report, a generalized expression for harmonic distortion of various dodecagonal PWM schemes is derived. Using this expression, one can determine the harmonic distortion magnitude for any dodecagonal PWM technique at a specified modulation index (MI) and boundary ani gle. The proposed DSV based PWM techniques are simulated in MATLAB Simulink environment and validated experimentally on a laboratory prototype. In the proposed DSVCPWM techniques, the dodecagonal space vector-based busclamping PWM technique shows a better harmonic profile than C12SVPWM and other DSVCPWM techniques at higher modulation indices. Similarly, based on the switching loss analysis, the proposed variable clamping PWM techniques have lower switching power loss than other dodecagonal PWM techniques. Better harmonic profile at higher MI and significant reduction in switching losses for lagging power factors make the variable clamping PWM technique as a good choice for the high-speed region of the motor drive applications. In addition to the development of dodecagonal space vector-based clamping PWM techniques, a novel space vector-based approach is introduced in this report, which selectively eliminates the lower order harmonics from the inverter output waveform based on voltage vector dwell time rearrangement. This technique uses a volt-second balance for control of fundamental voltage while using the dwell time rearrangement of active or zero vector in a sub-cycle to eliminate selected harmonic. The dwell time rearrangement concept is demonstrated for the hexagonal space vector to eliminate the fifth harmonic or seventh harmonic from the inverter output waveform. Further, this concept is implemented in a dodecagonal space vector structure to eliminate the eleventh harmonic or thirteenth harmonic. The proposed techniques are validated through the MATLAB Simulink environment, and their performance characteristics are compared with other space vector based PWM techniques in terms of harmonic magnitudes and voltage weighted harmonic distortion.
|National Institute of Technology Karnataka, Surathkal
|Department of Electrical and Electronics Engineering
|Investigations on Low Switching Frequency Pulse Width Modulation Techniques for Lower Order Harmonic Elimination and Switching Loss Reduction in Voltage Source Inverter Fed Induction Motor Drive Applications
|Appears in Collections:
|1. Ph.D Theses
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