Please use this identifier to cite or link to this item:
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBonthala S.
dc.contributor.authorUppoor Y.
dc.contributor.authorNayak A.
dc.contributor.authorPolineni S.
dc.contributor.authorBhat M.S.
dc.identifier.citationProceedings of the 2019 International Symposium on Embedded Computing and System Design, ISED 2019 , Vol. , , p. 78 - 83en_US
dc.description.abstractThis paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V. © 2019 IEEE.en_US
dc.titleDesign of High Resolution Delta Sigma Modulator in 180 nm CMOS technologyen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

Files in This Item:
There are no files associated with this item.

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.