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dc.contributor.authorNayak A.
dc.contributor.authorBonthala S.
dc.contributor.authorUppoor Y.
dc.contributor.authorBhat M.S.
dc.identifier.citation2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Proceedings , Vol. , , p. -en_US
dc.description.abstractThis paper presents two architectures of two-stage Operational Transconductance Amplifiers (OTAs). To achieve high gain, folded cascode topology is used. The first architecture uses an external bias which can be controlled independent of the OTA gain and bandwidth, while the second architecture uses a self-bias which reduces the power dissipation at the expense of restricted control over gain and bandwidth tuning. The two topologies are implemented using UMC 180 nm CMOS 1P9M technology. Both the architectures provide higher gain and consume less power in comparison to the previously published results. © 2019 IEEE.en_US
dc.titleDesign of High Gain Operational Transconductance Amplifiers in 180 nm CMOS technologyen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

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