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dc.contributor.authorSravani K.
dc.contributor.authorRao R.
dc.identifier.citationLecture Notes in Electrical Engineering , Vol. 700 , , p. 1543 - 1548en_US
dc.description.abstractThis paper proposes a new way of realizing the data paths for asynchronous domino logic gate-level pipeline styles. This novel approach improves the speed of the pipelines by preserving the latch-less feature of domino pipelines. In this work, the data paths of three asynchronous 16-bit adders based on APCDP, LP2/2, and HC-Hybrid pipelines are constructed using dual-rail domino cascode voltage switch (DDCVS) logic and simulated using cadence toolset in 90 nm technology. The adders based on DDCVS logic have exhibited higher performance and lower energy-delay square product compared to the adders based on domino logic. © 2021, Springer Nature Singapore Pte Ltd.en_US
dc.titleDDCVS Logic for Asynchronous Gate-Level Pipelined Circuitsen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

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