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dc.contributor.authorDavid S.-
dc.identifier.citationProceedings of the IEEE International Conference on VLSI Design pp. 394-399, 1998en_US
dc.description.abstractThe paper presents a pipelined parallel processor architecture design to implement the MD4 message digest algorithm which computes the message digest or the fingerprint of 128 bit fixed length, for any arbitrary length of input message. The processor implements the arithmetic, logic and circular shift operations by a pipelined parallel process. The architecture is designed to suit the design flexibility of the Xilinx Field Programmable Gate Arrays (FPGAs) The processor reads the message from an external RAM, 16-bit at a time and internal operations are performed with 32-bit data. The major advantage of the design is increased speed of computation and minimum hardware. The processor computes the digest with a speed approximately three times faster than the software version implemented in DSP processors.en_US
dc.subjectPipelined Parallel Processoren_US
dc.subjectXilinx FPGAen_US
dc.subjectMD4 Messageen_US
dc.titlePipelined Parallel Processor to implement MD4 Message digest algorithm on Xilinx FPGAen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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