Please use this identifier to cite or link to this item: https://idr.nitk.ac.in/jspui/handle/123456789/10964
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dc.contributor.authorNaik, B.S.
dc.contributor.authorSuresh, Y.
dc.contributor.authorVenkataramanaiah, J.
dc.contributor.authorPanda, A.K.
dc.date.accessioned2020-03-31T08:23:28Z-
dc.date.available2020-03-31T08:23:28Z-
dc.date.issued2019
dc.identifier.citationIET Power Electronics, 2019, Vol.12, 15, pp.3953-3963en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/10964-
dc.description.abstractIn this study, a novel nine-level modified T-type multilevel inverter (MT-MLI) with a simple capacitor balancing technique is proposed. The proposed MT-MLI circuit can generate higher levels with a single DC source and the minimum number of switching components. Each phase of the proposed topology contains ten switches and one flying capacitor (FC). The DC source voltage is divided into two parts with the help of capacitors. Phase disposition-sine pulse-width modulation technique is employed to regulate the DC-link capacitors and FC voltages. To reduce the control complexity of FC-based circuits, quarter-cycle selector is introduced to control the FC voltage within the given half fundamental cycle using redundant states, so an external capacitor charging setup is not required. Furthermore, to highlight the potential merits of the proposed MT-MLI, the comparison is made among state-of-the-art MLIs. Simulation verification of the MT-MLI is done using MATLAB/ Simulink, and then hardware verifications are done using the laboratory prototype setup with Opal-RT controller. Finally, adequate results are presented to validate the proposed MT-MLI. The Institution of Engineering and Technology 2019en_US
dc.titleDesign and implementation of a novel nine-level MT-MLI with a self-voltage-balancing switching techniqueen_US
dc.typeArticleen_US
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