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Results 21-30 of 39 (Search time: 0.005 seconds).
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Issue Date
Title
Author(s)
Supervisor(s)
2017
Triple reduced surface field drain extended MOS device design and its RF performance evaluation for sub-micron RF SoC platform
Somayaji, B.J.
;
Bhat, M.S.
-
2013
A fourth-order Partial Differential Equation model for multiplicative noise removal in images
Bini, A.A.
;
Bhat, M.S.
-
2016
An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC
Bhat, K.G.
;
Laxminidhi, T.
;
Bhat, M.S.
-
2013
A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
Lad, K.
;
Bhat, M.S.
-
2015
GSM and GUI Based Remote Data Logging System
Khan, S.R.
;
Nath, R.K.
;
Bhat, M.S.
-
2019
High Level Optimization Methodology for High Performance DSP Systems using Retiming Techniques
Mehra, H.
;
Bhat, M.S.
-
2010
Performance enhancement in high speed on-chip interconnect lines
Soorya, Krishna, K.
;
Bhat, M.S.
-
2014
Design of a triple band-notched circular monopole antenna for UWB applications
Reddy, B.C.
;
Shajahan, E.S.
;
Bhat, M.S.
-
2011
An adaptive total variation model with local constraints for denoising partially textured images
Bini, A.A.
;
Bhat, M.S.
;
Jidesh, P.
-
2017
A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry
Sharma, B.S.
;
Bhat, M.S.
-
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Sharma, B.S.
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Bhat, N.
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Hebbar, S.
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Khan, S.R.
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2010 - 2019
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