Browsing by Author Talawar, B.

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Showing results 9 to 27 of 27 < previous 
Issue DateTitleAuthor(s)Supervisor(s)
2019Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architecturesHalavar, B.; Pasupulety, U.; Talawar, B.-
2018Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chipHalavar, B.; Talawar, B.-
2018FPGA based NoC Simulation Acceleration Framework Supporting Adaptive RoutingParane, K.; Prabhu, Prasad, B.M.; Talawar, B.-
2017GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance imagesUpadhya, A.H.K.; Talawar, B.; Rajan, J.-
2019High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocksPrabhu, Prasad, B.M.; Parane, K.; Talawar, B.-
2019High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAsPrabhu, P.B.M.; Parane, K.; Talawar, B.-
2020LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGAParane, K.; Prabhu, Prasad, B.M.; Talawar, B.-
2018Machine Learning Based Framework to Predict Performance Evaluation of On-Chip NetworksKumar, A.; Talawar, B.-
2019MMAS on GPU for Large TSP InstancesYelmewad, P.; Kumar, A.; Talawar, B.-
2018Near Optimal Solution for Traveling Salesman Problem using GPUYelmewad, P.; Talawar, B.-
2015On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA Processors in Gem5 Full System SimulatorVikas, B.; Talawar, B.-
2020OP3DBFT: A power and performance optimal 3D BFT NoC architectureHalavar, B.; Talawar, B.-
2019Parallel iterative hill climbing algorithm to solve TSP on GPUYelmewad, P.; Talawar, B.-
2019A Support Vector Regression-Based Approach to Predict the Performance of 2D 3D On-Chip Communication ArchitecturesKumar, A.; Talawar, B.-
2018Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) ArchitecturesPasupulety, U.; Halavar, B.; Talawar, B.-
2018Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGASangeetha, G.S.; Radhakrishnan, V.; Prasad, P.; Parane, K.; Talawar, B.-
2020UPM-NoC: Learning based framework to predict performance parameters of mesh architecture in on-chip networksKumar, A.; Talawar, B.-
2019YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGASParane, K.; Prabhu, Prasad, B.M.; Talawar, B.-
2018YaNoC: Yet another network-on-chip simulation acceleration engine using FPGASParane, K.; Talawar, B.; Prabhu, Prasad, B.M.-