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Browsing by Author Prabhu, Prasad, B.M.

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Issue Date	Title	Author(s)	Supervisor(s)
2019	High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks	Prabhu, Prasad, B.M.; Parane, K.; Talawar, B.	-
2020	LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA	Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.	-
2019	YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS	Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.	-
2018	YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS	Parane, K.; Talawar, B.; Prabhu, Prasad, B.M.	-

Showing results 4 to 7 of 7 < previous