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Browsing by Author Parane, K.

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Issue Date	Title	Author(s)	Supervisor(s)
2018	Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA	Sangeetha, G.S.; Radhakrishnan, V.; Prasad, P.; Parane, K.; Talawar, B.	-
2019	YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS	Parane, K.; Prabhu, Prasad, B.M.; Talawar, B.	-
2018	YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS	Parane, K.; Talawar, B.; Prabhu, Prasad, B.M.	-

Showing results 8 to 10 of 10 < previous