Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques

Abstract

An intra-communication problem between the Intellectual Properties(IPs) caused by the growth of a number of cores on single chips in System-on-Chip(SoC) gave rise to new a system architecture called Network-on-Chip(NoC). The early stages of designing NoC can be done using cycle-accurate NoC simulators, but they become slow as the architecture size of NoC increases. Hence a machine learning framework is being proposed by considering two scenarios i,e. A fixed delay between the components and floorplan based delay among the components of NoC. This framework is modeled using distinct Machine Learning(ML) regression algorithms to predict performance parameters of NoCs considering uniform random and transpose traffic patterns. Complete performance analysis of Mesh NoC architecture can be done by using the proposed ML framework. Booksim simulator results are used to verify effectiveness of proposed framework and it showed an overall speedup of 2000× to 2500×. © 2019 IEEE.