High-Speed Multiplexed Feedback D Flip-Flop

Abstract

This work proposes a new high-speed architecture of a positive edge-triggered D flip-flop. A multiplexed feedback push-pull network is used to decrease the clock to q delay and setup time of the flip-flop. This multiplexed network acts as feedback as well as a charging network. It was observed that this architecture reduces the propagation delay by 21 and 23% compared to push-pull isolation and conventional D flip-flop. The proposed D flip-flop design can be utilized in critical paths of a pipelined system to improve the speed. The circuit is designed on 180 nm technology and tested for load at various process corners using the Cadence Virtuoso tool. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.