Improving Reliability in Spidergon Network on Chip-Microprocessors

Abstract

Aggressive technology scaling continues to make networks-on-chip (NoCs) vulnerable to failures that relentlessly result in reliability concerns and unexpected system performance degradation. Therefore, there is an urgent demand for an effective test methodology that does not only improve the NoC's reliability but also prevent the system from being trapped into system-level failure modes. This paper presents a low-cost test scheme that addresses stuck-at faults in the communication channels of a Spidergon NoC. A built-in-self-test (BIST) method is presented to quickly detect the faults and reduce the affected application packets. The present test method is combined with a scheduling technique that together minimizes the test cost metrics, e.g., reduces 81.25% test time making the current test solution to become at least 5× faster. Furthermore, the solution shows less influence on system performance. © 2020 IEEE.