The problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGA's) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices of one or more connected components together. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Both cost optimal and delay optimal mappings are supported. The objective in cost optimal mapping is to cover a given data path network with minimum number of CLB's. Similarly in delay optimal mapping, the objective is to reduce the number of CLB levels in the critical combinational logic paths. Implementation of these mapping techniques with LUT based FPGA's as target technology results in a significant reduction in cost (CLB count) and critical path delays (CLB levels). © 1998 IEEE.

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dc.contributor.authorNaseer, A.R.
dc.contributor.authorBalakrishnan, M.
dc.contributor.authorKumar, A.
dc.date.accessioned2026-02-05T11:00:33Z
dc.date.issuedDirect mapping of RTL structures onto LUT-based FPGA's
dc.description.abstract1998
dc.identifier.citationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998, 17, 7, pp. 624-631
dc.identifier.issn2780070
dc.identifier.urihttps://doi.org/10.1109/43.709401
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/28038
dc.subjectBoolean network
dc.subjectData path
dc.subjectHigh level synthesis
dc.subjectLook up table
dc.subjectRTL structure
dc.subjectTechnology mapping
dc.subjectApplication specific integrated circuits
dc.subjectBoolean functions
dc.subjectCombinatorial circuits
dc.subjectData structures
dc.subjectElectric network synthesis
dc.subjectField programmable gate arrays
dc.subjectLogic gates
dc.subjectSequential circuits
dc.subjectMathematical techniques
dc.titleThe problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGA's) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices of one or more connected components together. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Both cost optimal and delay optimal mappings are supported. The objective in cost optimal mapping is to cover a given data path network with minimum number of CLB's. Similarly in delay optimal mapping, the objective is to reduce the number of CLB levels in the critical combinational logic paths. Implementation of these mapping techniques with LUT based FPGA's as target technology results in a significant reduction in cost (CLB count) and critical path delays (CLB levels). © 1998 IEEE.

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