Design of CMOS RF receiver front-end for IEEE 802.11b
| dc.contributor.author | Konidala, N. | |
| dc.contributor.author | Bhat, M.S. | |
| dc.date.accessioned | 2026-02-06T06:40:56Z | |
| dc.date.issued | 2008 | |
| dc.description.abstract | This paper presents the design of a fully integrated receiver front-end for a 2.4GHz RF transceiver. The proposed receiver front end (Low-Noise Amplifier and Mixer) is based on a direct conversion architecture designed in 0.18μm CMOS technology. The chip provides a down conversion gain to the 50 MHz IF of 13.2 dB, SSB Noise Figure (NF) of 7.65 dB and a 3rd-order input intercept point (IIP<inf>3</inf>) of -14.6dBm consuming 50.6mW at1.8 V. ©2008 IEEE. | |
| dc.identifier.citation | 2008 International Conference on Electronic Design, ICED 2008, 2008, Vol., , p. - | |
| dc.identifier.uri | https://doi.org/10.1109/ICED.2008.4786700 | |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/33258 | |
| dc.title | Design of CMOS RF receiver front-end for IEEE 802.11b |