An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET

dc.contributor.authorMathew, S.
dc.contributor.authorChennamadhavuni, S.
dc.contributor.authorRao, R.
dc.date.accessioned2026-02-04T12:24:35Z
dc.date.issued2024
dc.description.abstractIn this work, Fourier series-based analytical models for threshold voltage (V<inf>th</inf>) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of V<inf>th</inf> for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm. © 2024 Elsevier Ltd
dc.identifier.citationMicro and Nanostructures, 2024, 191, , pp. -
dc.identifier.issn27730131
dc.identifier.urihttps://doi.org/10.1016/j.micrna.2024.207848
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/21038
dc.publisherElsevier Ltd
dc.subjectAnalytical models
dc.subjectFinFET
dc.subjectFourier series
dc.subjectSilicon on insulator technology
dc.subjectChannel potential
dc.subjectChannel potential model
dc.subjectCurrent conduction
dc.subjectDIBL
dc.subjectFin field-effect transistors
dc.subjectPotential modeling
dc.subjectSilicon on insulator
dc.subjectSilicon on insulator junctionless fin field effect transistor
dc.subjectSub-threshold swing
dc.subjectSubthreshold
dc.subjectThreshold voltage
dc.titleAn improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET

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