Hardware implementation of dual-tree wavelet transform based image reconstruction
| dc.contributor.author | Sudhakar, H. | |
| dc.contributor.author | Kalam, L.M. | |
| dc.contributor.author | Muralitharan, S. | |
| dc.contributor.author | Deepu, S.P. | |
| dc.contributor.author | Sumam David, S.S. | |
| dc.date.accessioned | 2026-02-06T06:36:55Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | Real-time implementations of image processing algorithms on embedded platforms are gaining importance. In this paper, we propose an Application Specific Integrated Circuit (ASIC) architecture for the perfect reconstruction of images using wavelets with a view to extending this to denoising and feature extraction of images. An architecture that implements the Dual-Tree Wavelet Transform is presented. The architecture features a 128x128 single-port block memory and its addressing schemes, a simple upsampling/downsampling method and a folding and adding mechanism. It is implemented using 180nm technology. The results show perfect reconstruction of 128x128 grayscale images with up to 1-bit error in pixel values when compared to the corresponding input images. © 2021 IEEE | |
| dc.identifier.citation | Proceedings - IEEE International Symposium on Circuits and Systems, 2020, Vol.2020-October, , p. - | |
| dc.identifier.issn | 2714310 | |
| dc.identifier.uri | https://doi.org/ | |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/30753 | |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
| dc.title | Hardware implementation of dual-tree wavelet transform based image reconstruction |