Accurate Router Level Estimation of Network-on-Chip Architectures using Learning Algorithms

Abstract

The problem of intra-communication between the Intellectual Properties(IPs) due to the rise in the amount of cores on single chips in System-on-Chip(SoC). Network-on-Chips(NoCs) has emerged as a reliable on-chip communication framework for Chip Multiprocessors and SoCs. Estimating NoC power and performance in the early stages has become crucial. We employ Machine Learning(ML) approaches to estimate architecture-level on-chip router models and performance. Experiments were carried out with distinct topology sizes with various virtual channels, injection rates, and traffic patterns. Booksim and Orion simulators are used to validate the results. Approximately 6% to 8% prediction error and a minimum speedup of 1500 × to 2000 × were shown in the framework. © 2019 IEEE.